Publications

Journal articles

• M. Minea, C. Izbasa, C. Jebelean. Experience with Formal Verification of SDL Protocols. "Computing" International Scientific Journal, vol. 2, issue 3, 2003. PDF
• R. Kurshan, V. Levin, M. Minea, D. Peled, H. Yenigün. Combining software and hardware verification techniques. Formal Methods in System Design, vol. 21, no. 3, pp. 251-280, 2002. PDF
• E. M. Clarke, O. Grumberg, M. Minea, D. Peled. State space reduction using partial order techniques. Software Tools for Technology Transfer, vol. 2, no. 3, 1999, pp. 279-287. PDF
• S. Campos, E. M. Clarke, M. Minea. Symbolic techniques for formally verifying industrial systems. Science of Computer Programming, vol. 29 no. 1-2, July 1997, pp. 79-98. PDF
• S. Campos, E. M. Clarke, W. Marrero, M. Minea, and H. Hiraishi. Temporal verification of real-time systems. IEICE Transactions on Information and Systems (Japan), vol. 78-D, no. 7, pp. 796-801, July 1995. PDF

Refereed conference/workshop articles and book chapters

• A. Armando, W. Arsac, T. Avanesov, M. Barletta, A. Calvi, A. Cappai, R. Carbone, Y. Chevalier, L. Compagna, J. Cuéllar, G. Erzse, S. Frau, M. Minea, S. Mödersheim, D. von Oheimb, G. Pellegrino, S. E. Ponta, M. Rocchetto, M. Rusinowitch, M. Torabi Dashti, M. Turuani, L. Viganň. The AVANTSSAR Platform for the Automated Validation of Trust and Security of Service-Oriented Architectures. Proceedings of the 18^th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS)}, LNCS vol. 7214, pp. 267-282, Springer, 2012. PDF (© Springer Verlag)
• M. Balint, M. Minea. Automatic Inference of Model Fields and their Representation. Proceedings of the 13^th Workshop on Formal Techniques for Java-like Programs, 2011. PDF (© ACM)
• R. Carbone, M. Minea, S.A. Mödersheim, S.E. Ponta, M. Turuani, L. Viganò. Towards Formal Validation of Trust and Security in the Internet of Services. Future Internet Assembly: Achievements and Technological Promises, Lecture Notes in Computer Science, vol. 6656, pp. 193-207, 2011. PDF (© Springer Verlag)
• B. Groza, M. Minea. Formal modelling and automatic detection of resource exhaustion attacks. Proc. 6^th ACM Symposium on Information, Computer and Communications Security (ASIACCS), pp. 326-333, 2011 PDF (© ACM)
• B. Groza, M. Minea. Customizing protocol specifications for detecting resource exhaustion and guessing attacks. Proc. 9^th International Symposium on Formal Methods for Components and Objects, 2010 PDF (© Springer Verlag)
• B. Groza, M. Minea. A formal approach for automated reasoning about off-line and undetectable on-line guessing (short paper). Proc. 14^th International Conference on Financial Cryptography and Data Security, LNCS vol. 6052, pp. 391-399, 2010 PDF (© Springer Verlag)
• D. Dig, M. Tarce, C. Radoi, M. Minea, R. Johnson. ReLooper: Refactoring for Loop Parallelism in Java. OOPSLA'09 companion, PDF. See also extended version as UIUC Technical Report
• B. Groza, M. Minea. A calculus to detect guessing attacks. Proc. 12th Information Security Conference, LNCS vol. 5739, pp. 59-67, 2009 PDF (© Springer Verlag)
• P. Bulychev, M. Minea. An evaluation of duplicate code detection using anti-unification. Proc. 3^rd International Workshop on Software Clones. PDF
• P. Bulychev, M. Minea. Duplicate code detection using anti-unification. Proc. of the SyRCoSE Workshop, St. Petersburg, 2008 PDF
• J. Elmqvist, S. Nadjm-Tehrani, M. Minea. Safety Interfaces for Component-Based Systems. Proc. 24^th International Conference on Computer Safety, Reliability and Security (SAFECOMP), LNCS vol. 3688, pp. 246--260, Springer, 2005 PDF
• D. Beauquier, M. Duflot, M. Minea, A probabilistic property-specific approach to information flow, Proc. Mathematical Methods, Models and Architectures for Computer Networks Security, LNCS vol. 3685, pp. 206--220, Springer, 2005 PDF
• B. Genest, M. Minea, A. Muscholl, D. Peled. Specifying and verifying partial order properties using template MSCs. Proceedings of the 7^th International Conference on Foundations of Software Science and Computation Structures (FoSSaCS), LNCS vol. 2987, pp. 195-210, Springer, 2004 PDF
• M. Minea, C. Izbasa, C. Jebelean. Experience with Formal Verification of SDL Protocols. Proceedings of the NATO Advanced Research Workshop on Concurrent Information Processing and Computing, pp. 185-192, Al.I.Cuza University Press, Romania, 2003. PDF
• T.A. Henzinger, M. Minea, V. Prabhu. Assume-guarantee reasoning for hierarchical hybrid systems. Proceedings of the 4th International Workshop on Hybrid Systems: Computation and Control, LNCS vol. 2034, pp.275-290, Springer, 2001. PDF
• M. Minea. Partial order reduction for model checking of timed automata. Proceedings of the 10th International Conference on Concurrency Theory, LNCS vol. 1664, pp.431-446, Springer, 1999. PDF
• S. Campos, M. Teixeira, M. Minea, A. Kuehlmann, E. Clarke. Model checking semi-continuous time models using BDDs. Proceedings of FLoC99 Workshop on Symbolic Model Checking, Elsevier ENTCS vol. 23 no. 2, pp. 75-88, 1999. PDF
• R. Kurshan, V. Levin, M. Minea, D. Peled, H. Yenigün. Static partial order reduction. Proceedings of the 4th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, LNCS 1384, pp. 345-357, Springer, 1998. PDF
• S. Jha, Y. Lu, M. Minea, E. M. Clarke. Equivalence checking using abstract BDDs. Proceedings of the International Conference on Computer Design, pp. 332-337, IEEE Computer Society Press, 1997. PDF
• S. Campos, E. Clarke, M. Minea. The Verus tool: a quantitative approach to the formal verification of real-time systems. Proceedings of the 9^th International Conference on Computer Aided Verification, LNCS vol. 1254, pp. 452-455, Springer, 1997. PDF
• S. Campos, E. Clarke, W. Marrero and M. Minea. Verifying the performance of the PCI local bus using symbolic techniques. Proceedings of the International Conference on Computer Design, pp. 72-78, IEEE Computer Society Press, 1995 PDF
• S. Campos, E. Clarke, W. Marrero and M. Minea. Verus: a tool for quantitative analysis of finite-state real-time systems. Proceedings of the Workshop on Languages, Compilers, and Tools for Real-Time Systems, ACM SIGPLAN Notices, vol. 30, no. 11, pp. 70-78, 1995. PDF
• S. Campos, E. Clarke, W. Marrero and M. Minea. Timing analysis of industrial real-time systems. Proceedings of the Workshop on Industrial-Strength Formal Specification Techniques, pp. 97-107, 1995. PDF
• S. Campos, E. Clarke, W. Marrero, M. Minea, H. Hiraishi. Computing quantitative characteristics of finite-state real-time systems. Proceedings of the Real-Time Systems Symposium, pp. 266-270, IEEE Computer Society Press, 1994. PDF
• P. Eles, K. Kuchcinski, Z. Peng, M. Minea. Synthesis of VHDL concurrent processes. Proceedings of EURO-DAC'94 with EURO-VHDL'94, pp. 540-545, IEEE Computer Society Press, 1994. PDF
• P. Eles, K. Kuchcinski, Z. Peng, M. Minea. Synthesis of VHDL Subprograms and Processes in the CAMAD System. Proceedings of the Workshop on Design Methodologies and Signal Processing, Gliwice-Cracow, Poland, pp. 359-366, 1993.
• P. Eles, K. Kuchcinski, Z. Peng, M. Minea. Synthesis of VHDL concurrent processes. Fifth Swedish Workshop on Computer Systems Architecture, DSA-93, Lund, pp. 32-33, 1993.
• P. Eles, M. Minea. VHDL and the High Level Synthesis of Digital Circuits. Some Principles and Implementation. Conference Preprints of the 9th International Conference on Control Systems and Computer Science (CSCS 9), Politehnica University of Bucharest, vol. I, pp. 470-475, 1993.
• P. Eles, K. Kuchcinski, Z. Peng, M. Minea. Compiling VHDL into a high-level synthesis design representation. Proceedings of EURO-DAC'92 with EURO-VHDL'92, IEEE Computer Society Press, pp. 604-609, 1992. PDF

Other articles

• R. Kurshan, V. Levin, M. Minea, D. Peled, H. Yenigün. Verifying hardware in its software context. Proc. of the IEEE International Conference on Computer Aided Design, pp. 742-749 IEEE Computer Society Press, pp. 742-749, 1997 (invited conference article) PDF
• S. Campos, E. Clarke, M. Minea. Analysis of Real-Time Systems Using Symbolic Techniques. In Formal Methods for Real-Time Computing, Constance Heitmeyer and Dino Mandrioli (eds.), pp. 217-235, John Wiley, 1997. (refereed book chapter)

Technical reports

• M. Minea. Partial Order Reduction for Verification of Timed Systems. Ph.D. Thesis, Carnegie Mellon University, Report CMU-CS-00-102, December 1999. 124 pp. PDF
• M. Minea. A VHDL Compiler for a High-Level Synthesis System. Diploma Thesis. Research Report LiTH-IDA-R-93-23, Linköping University, June 1993. 65 pp.